Title :
High-order delta-sigma modulator with switched-current feedback memory cell
Author :
Sung, Guo-Ming ; Yu, Chih-Ping ; Hou, Yueh-Hung
Author_Institution :
Dept. of Electr. Eng., Nat. Taipei Univ. of Technol., Taipei
fDate :
Nov. 30 2008-Dec. 3 2008
Abstract :
In this paper, we present a design of the fully differential high-order multi-stage noise shaping (MASH) delta-sigma modulator (DSM). To improve the transmission error, a current feedback method is used in the proposed switched-current feedback memory cell (FMC) to decrease the input impedance. Furthermore, the entire memory cell is designed in a coupled differential replicate (CDR) form to eliminate the clock feedthrough (CFT) error. Note that the DSM is simulated with TSMC 0.18 mum CMOS process technology. And that, the simulation results reveal that the peak signal to noise plus distortion ratio (SNDR) is 83 dB at 10.24 MHz sampling rate with 40 kHz bandwidth, and the power dissipation is 12.3 mW.
Keywords :
CMOS memory circuits; circuit feedback; delta-sigma modulation; switched current circuits; TSMC CMOS process technology; coupled differential replicate form; frequency 40 kHz; high-order delta-sigma modulator; multistage noise shaping DSM; size 0.18 mum; switched-current feedback memory cell design; transmission error; CMOS process; CMOS technology; Clocks; Couplings; Delta modulation; Distortion; Feedback; Impedance; Multi-stage noise shaping; PSNR;
Conference_Titel :
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
Conference_Location :
Macao
Print_ISBN :
978-1-4244-2341-5
Electronic_ISBN :
978-1-4244-2342-2
DOI :
10.1109/APCCAS.2008.4746228
