A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs

Author

Chio, U-Fat ; Wei, He-Gong ; Zhu, Yan ; Sin, Sai-Weng ; U, Seng-Pan ; Martins, R.P.

Author_Institution

Analog & Mixed Signal VLSI Lab., Univ. of Macau, Macao

fYear

2008

fDate

Nov. 30 2008-Dec. 3 2008

Firstpage

1164

Lastpage

1167

Abstract

Novel self-timing switch-driving registers for high-speed successive approximation register (SAR) ADC is proposed. This circuit can provide fast charging path from comparator output to DAC array of SAR ADC and store the comparison results simultaneously at each approximation bit-cycle. The propagation delay from input to output of the register is about 60 ps only in a 90 nm CMOS process. By using this technique, the 5-bit SAR ADC achieves 30.3 dB SNDR with 285 MS/s high sampling-rate, power consumption is 10.5 mW.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); CMOS process; DAC array; approximation bit-cycle; comparator output; high-speed SAR ADC; high-speed successive approximation register ADC; noise figure 30.3 dB; power 10.5 mW; power consumption; precharge-evaluate logic; propagation delay; self-timing switch-driving register; CMOS logic circuits; Capacitors; Clocks; Latches; Logic circuits; Propagation delay; Shift registers; Strontium; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on

Conference_Location

Macao

Print_ISBN

978-1-4244-2341-5

Electronic_ISBN

978-1-4244-2342-2

Type

conf

DOI

10.1109/APCCAS.2008.4746232

Filename

4746232