A CMOS low-voltage fully differential sample-and-hold circuit

Author

Lu, Chi-Chang ; Tung, Wei-Xiang ; Huang, Chien-Kuo

Author_Institution

Dept. of Electr. Eng., Nat. Formosa Univ., Huwei

fYear

2008

fDate

Nov. 30 2008-Dec. 3 2008

Firstpage

1188

Lastpage

1191

Abstract

A new technique for realizing a CMOS low-voltage fully differential sample-and-hold circuit is presented. A low-voltage technique is proposed for CMOS sample-and-hold circuit that avoids the use of low-threshold voltage process, on-chip clock voltage doubler, bootstrapped switch, or switched-opamp technique. For 2.5 MHz input signal frequency, the proposed sample-and-hold circuit exhibits a THD of -62 dB for 1.0 V_pp input signal at 25 MHz sampling rate. Simulation results are given to demonstrate the potential advantage of the new technique.

Keywords

CMOS integrated circuits; circuit simulation; integrated circuit design; low-power electronics; sample and hold circuits; CMOS sample and hold circuit; bootstrapped switch; frequency 2.5 MHz; fully differential; input signal frequency; low threshold voltage process; low voltage technique; on chip clock voltage doubler; switched opamp technique; CMOS process; Circuit simulation; Clocks; MOSFETs; Operational amplifiers; Sampling methods; Switches; Switching circuits; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on

Conference_Location

Macao

Print_ISBN

978-1-4244-2341-5

Electronic_ISBN

978-1-4244-2342-2

Type

conf

DOI

10.1109/APCCAS.2008.4746238

Filename

4746238