A process- and temperature- insensitive current-controlled delay generator for sampled-data systems

This paper proposes a process- and temperature-insensitive current-controlled delay generator which can be widely used in sampled-data systems. The delay generator provides a large tunable range by adjusting the control current and load capacitance. Full transistor-level simulations, including process corner and Monte-Carlo analysis, are presented. The delay generator is designed in 90 nm CMOS technology and consumes 330 muW power from a 1.2 V power supply, at a typical case of using 10 muA control current and 30 fF load capacitance. The process corner simulation results exhibit a typical delay of 2.09 ns with a corner variation of -7.1% / +7.6%. The 500-times process Monte-Carlo simulation obtains a mean of 2.09 ps with a standard-deviation (sigma) of 28.9 ps (1.38%).