Title :
Logic synthesis of asynchronous circuits
Author_Institution :
Centre Suisse d´´Electron. et de Microtech., Neuchatel, Switzerland
Abstract :
A synthesis method and a CAD program to provide racefree asynchronous CMOS circuits that are independent of the internal and output delays are presented. The method minimizes the number of transitions between stable states and the number of gates, providing new cells for fast and low-power integrated circuits. Without any additional cost, the circuit will present neither critical races nor hazards (no race exists between any two variables), and the circuit is suitable for integration of low-power or very fast applications
Keywords :
CMOS integrated circuits; asynchronous sequential logic; integrated logic circuits; logic CAD; CAD program; low-power integrated circuits; racefree asynchronous CMOS circuits; static circuits; synthesis method; Asynchronous circuits; CMOS logic circuits; Circuit synthesis; Combinational circuits; Delay; Hazards; Integrated circuit synthesis; Logic circuits; Logic gates; Semiconductor device modeling;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124831
