Title :
Architecture of an image rendering co-processor for MPEG-4 systems
Author :
Berekovic, M. ; Pirsch, P. ; Selinger, T. ; Wels, K.-I. ; Miro, C. ; Lafage, A. ; Heer, C. ; Ghigo, G.
Author_Institution :
Lab. fur Informationstechnol., Hannover Univ., Germany
Abstract :
The TANGRAM VLSI co-processor is intended as a building block for use in system-on-chip (SOC) designs for the versatile MPEG-4 multimedia standard. It is designed to perform the computation intensive final step of MPEG-4 video decoding: compositing of scenes at the display. This includes warping and alpha blending of multiple full-screen video textures in real-lime. TANGRAM consists of a RISC control processor and multiple powerful arithmetic units that perform rendering calculations directly in hardware. This hybrid architecture enables adaptation to changes in algorithms or software support for different video-formats. Communication to a host CPU and video decoding hardware is done via the very common PI-bus on-chip interface. TANGRAM directly interfaces with the ITU-R601/656 digital video output. VHDL implementation and synthesis for a 0.35 μ standard-cell library provide an estimate of 100 MHz achievable clock-frequency (worst-case), 52 mm2 overall area and 1 Watt power dissipation. TANGRAM has sufficient performance for rendering of MPEG-4 Main Profile@Layer3 scenes (CCIR)
Keywords :
VLSI; coprocessors; decoding; image texture; multimedia computing; reduced instruction set computing; rendering (computer graphics); video signal processing; 0.35 micron; 1 W; 100 MHz; MPEG-4 systems; Main Profile@Layer3 scenes; PI-bus on-chip interface; RISC control processor; SOC designs; TANGRAM VLSI co-processor; VHDL implementation; achievable clock-frequency; alpha blending; arithmetic units; image rendering co-processor; multimedia standard; power dissipation; rendering calculations; scene compositing; video decoding; Computer architecture; Coprocessors; Decoding; Hardware; Layout; MPEG 4 Standard; Multimedia systems; Rendering (computer graphics); System-on-a-chip; Very large scale integration;
Conference_Titel :
Application-Specific Systems, Architectures, and Processors, 2000. Proceedings. IEEE International Conference on
Conference_Location :
Boston, MA
Print_ISBN :
0-7695-0716-6
DOI :
10.1109/ASAP.2000.862374
