A low complexity modulo 2n+1 squarer design

Modulo 2ⁿ+1 squaring has been used in various applications like cryptography and Fermat number transform. Arithmetic modulo 2ⁿ+1 is also known to be the most time critical among the three residue channels in the prevalent {2ⁿ -1, 2ⁿ, 2ⁿ+1} based residue number system (RNS). In order to speed up modulo 2ⁿ+1 operation, the diminished-1 number representation is widely employed. However the use of diminished-1 representation results in area overhead and increased execution delay. In this paper, we present a design of modulo 2ⁿ+1 squarer using weighted binary representation. Our synthesis results based on TSMC 0.18 m CMOS standard cell library indicate that the proposed squarer offers significant area and delay savings of up to 25% and 11%, respectively.