Title :
A low complexity modulo 2n+1 squarer design
Author :
Muralidharan, Ramya ; Chang, Chip-Hong ; Jong, Ching-Chuen
Author_Institution :
Centre for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore
fDate :
Nov. 30 2008-Dec. 3 2008
Abstract :
Modulo 2n+1 squaring has been used in various applications like cryptography and Fermat number transform. Arithmetic modulo 2n+1 is also known to be the most time critical among the three residue channels in the prevalent {2n -1, 2n, 2n+1} based residue number system (RNS). In order to speed up modulo 2n+1 operation, the diminished-1 number representation is widely employed. However the use of diminished-1 representation results in area overhead and increased execution delay. In this paper, we present a design of modulo 2n+1 squarer using weighted binary representation. Our synthesis results based on TSMC 0.18 m CMOS standard cell library indicate that the proposed squarer offers significant area and delay savings of up to 25% and 11%, respectively.
Keywords :
matrix algebra; residue number systems; CMOS standard cell library; Fermat number transform; arithmetic modulo; cryptography; diminished-1 number representation; low complexity modulo squarer design; residue number system; weighted binary representation; Arithmetic; Concurrent computing; Cryptography; Delay; Embedded system; Libraries; Matrices;
Conference_Titel :
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
Conference_Location :
Macao
Print_ISBN :
978-1-4244-2341-5
Electronic_ISBN :
978-1-4244-2342-2
DOI :
10.1109/APCCAS.2008.4746265
