Title :
A 550 Mb/s radix-4 bit-level pipelined 16-state 0.25-μm CMOS Viterbi decoder
Author :
Gierenz, V.S. ; Weiss, O. ; Noll, T.G. ; Carew, I. ; Ashley, J. ; Karabed, R.
Author_Institution :
Inst. of Technol., Tech. Hochschule Aachen, Germany
Abstract :
In todays high-speed disk drive read channel ICs maximum likelihood detection using the Viterbi algorithm is a key component in reconstructing digital data sequences. The presented Viterbi decoder was realized in a 0.25 μm CMOS technology. Using the proposed comparison approach, it achieves a throughput rate of 550 Mb/s
Keywords :
CMOS digital integrated circuits; Viterbi decoding; application specific integrated circuits; digital signal processing chips; disc drives; high-speed integrated circuits; maximum likelihood detection; pipeline processing; 0.25 micron; 550 Mbit/s; CMOS Viterbi decoder; Viterbi algorithm; digital data sequences; high-speed disk drive read channel IC; maximum likelihood detection; radix-4 bit-level pipelined decoder; Arithmetic; CMOS technology; Digital integrated circuits; Disk drives; High speed integrated circuits; Maximum likelihood decoding; Maximum likelihood detection; Pipeline processing; Throughput; Viterbi algorithm;
Conference_Titel :
Application-Specific Systems, Architectures, and Processors, 2000. Proceedings. IEEE International Conference on
Conference_Location :
Boston, MA
Print_ISBN :
0-7695-0716-6
DOI :
10.1109/ASAP.2000.862390
