An efficient architecture for HWT using sparse matrix factorisation and DA principles

Matrix computations are very important in image processing applications. Processing large images or matrices is computationally intensive, power hungry and requires a large amount of memory. This paper discusses the hardware implementation of a factorisation based approach for Haar wavelet transform (HWT) on reconfigurable hardware using distributed arithmetic (DA) principles. The proposed architectures can be integrated into a multiresolution based system for automatic detection and segmentation of tumour in medical images. Two factorisation methodologies are presented and their impact on FPGA implementation is addressed in terms of different resources required and performance achieved.