Design and analysis of a high performance AES processor

This paper presents the design of a high performance AES processor. An optimized AES algorithm without sacrificing its security features is used to design the processor. The proposed design is secured against all kinds of attacks. The design of the processor is simulated on the FPGA platform. Simulation results ensure its proper functionality. Due to a number of unique design consideration, the processor outperforms all other existing solutions in terms of latency which is an important factor for real time operation. The speed performance of the processor is also analyzed and compared with that of other researchers in ASIC technology which also proves its superiority over them.