Design of off-chip capacitor-free CMOS low-dropout voltage regulator

An off-chip capacitor-free CMOS low-dropout voltage regulator (LDO) for full on chip power management solution is presented. The proposed structure based on modified nested Miller compensation and transient enhancement network provides both fast load transient response and full load stability. For a pulsed load current between 0.5 mA and 50 mA, it is able to recover within ~3.5 mus and a less than 115 mV overshoots and undershoots of the output voltage is recorded for the most critical scenario. The total internal compensation capacitors are as small as 2.5 pF while the load capacitor can be as large as 100 pF. The idea has been implemented in CSMC 0.5 mum standard CMOS process and the total active chip area is 460 mum times 110 mum which makes it especially suitable for system-on-chip applications.