Title :
A 16-bit×16-bit MAC design using fast 5:2 compressors
Author :
Kwon, Ohsang ; Nowka, Kevin ; Swartzlander, Earl E.
Author_Institution :
Texas Univ., Austin, TX, USA
Abstract :
3:2 counters and/or 4:2 compressors have been widely used for multiplier implementations. In this paper, a new logical decomposition is derived for fast 5:2 compressor and is proposed to be used for 16-bit×16-bit MAC designs. In addition, when the accumulator output is in carry-save form, one row in partial product matrix can be eliminated prior to the partial product reduction process. These new methods are combined and explained with 16-bit×16-bit 2´s complement MAC (multiply and accumulate) designs. The use of the new 5:2 compressor leads to 14% speed improvement in the MAC design over the conventional designs using 4:2 compressors and 3:2 counters
Keywords :
adders; carry logic; digital arithmetic; multiplying circuits; 16 bit; MAC design; accumulator output; carry-save form; logical decomposition; multiplier implementations; partial product matrix; partial product reduction process; two´s complement; Compressors; Counting circuits;
Conference_Titel :
Application-Specific Systems, Architectures, and Processors, 2000. Proceedings. IEEE International Conference on
Conference_Location :
Boston, MA
Print_ISBN :
0-7695-0716-6
DOI :
10.1109/ASAP.2000.862394
