An analytical model for sidewall parasitic capacitance of nano-scale trench isolated MOSFETs

This paper presents a physics-based, analytical model for sidewall parasitic capacitance of nano-scale MOSFETs. Trench isolated MOSFETs have been considered in the 90 nm technology node. An analytical expression for the trench oxide parasitic capacitance is derived by taking into account the enhanced depletion depth caused due to gate fringing field at the trench oxide sidewalls and dopant redistribution in the channel. The sidewall parasitic capacitance is calculated using conformal mapping technique. The developed model has been validated by comparing the results predicted from the derived model with simulation data and with a similar model available in literature. It has been demonstrated that our model determines more correctly the parasitic capacitance of nano-scale devices compared to the existing model.