DocumentCode :
2328469
Title :
Contention-conscious transaction ordering in embedded multiprocessors
Author :
Khandelia, Mukul ; Bhattacharyya, Shuvra S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
fYear :
2000
fDate :
2000
Firstpage :
276
Lastpage :
285
Abstract :
This paper explores the problem of efficiently ordering interprocessor communication operations in statically-scheduled multiprocessors for iterative dataflow graphs. In most digital signal processing applications, the throughput of the system is significantly affected by communication costs. By explicitly modeling these costs within an effective graph-theoretic analysis framework, we show that ordered transaction schedules can significantly outperform self-timed schedules even when synchronization costs are low. However, we also show that when communication latencies are non-negligible, finding an optimal transaction order given a static schedule is an NP-complete problem, and that this intractability holds both under iterative and non-iterative execution. We develop new heuristics for finding efficient transaction orders, and perform an experimental comparison to gauge the performance of these heuristics
Keywords :
data flow graphs; embedded systems; multiprocessing systems; processor scheduling; signal processing; synchronisation; DSP applications; NP-complete problem; communication costs; communication latencies; contention-conscious transaction ordering; costs modeling; digital signal processing applications; embedded multiprocessors; graph-theoretic analysis framework; heuristics; interprocessor communication operations; iterative DFGs; iterative dataflow graphs; optimal transaction order; ordered transaction schedules; statically-scheduled multiprocessors; synchronization costs; system throughput; Cost function; Degradation; Delay; Digital signal processing; Educational institutions; Processor scheduling; Programming profession; Runtime; Signal design; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Application-Specific Systems, Architectures, and Processors, 2000. Proceedings. IEEE International Conference on
Conference_Location :
Boston, MA
ISSN :
2160-0511
Print_ISBN :
0-7695-0716-6
Type :
conf
DOI :
10.1109/ASAP.2000.862398
Filename :
862398
Link To Document :
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