A top-down, mixed-level design methodology for CT BP ΔΣ modulator using verilog-A

This paper presents a design methodology of a continuous-time (CT) Band-pass (BP) DeltaSigma modulator which can improve the design procedure. The proposed top-down, mixed-level design platform is implemented under Cadencepsilas Spectre environment using Verilog-A. A 2^nd order CT BP DeltaSigma modulator for WCDMA applications. The central frequency of this modulator is at 100 MHz and the quantizer operates at 400 MHz clock frequency. The modulator is designed using TSMC 0.35 mum CMOS technology with a supply voltage of 3.3 V. The simulated maximum SNDR is 40 dB for a 3.84 MHz bandwidth, which corresponds to a resolution of 6 bits.