DocumentCode
2329033
Title
Transformation-based layout optimization
Author
Hojati, Ramin ; Chen, Duan-Ping
Author_Institution
Cadence Design Syst. Inc., San Jose, CA, USA
fYear
1990
fDate
13-16 May 1990
Abstract
An approach to layout optimization that involves invoking a set of transformations on an initial symbolic layout is presented. The tools work well together, providing a high degree of user-controllability. The tools run on selected areas or the whole chip, honor the user´s modifications, perform with partial layouts and ERC/LVS errors, and have separate and clearly defined optimizations. The tools are fast and practical. Using these transformations, the quality of the layout of six industrial, block-oriented design is greatly improved. On average, the routing area is reduced by 15%, the number of contacts by 38%, and the wire length by 11%
Keywords
circuit layout CAD; optimisation; ERC/LVS errors; compaction; defined optimizations; initial symbolic layout; module generation; number of contacts reduction; partial layouts; routing area reduction; set of transformations; user-controllability; wire length reduction; Automatic control; Controllability; Design optimization; Error correction; Interference constraints; Layout; Rivers; Routing; Testing; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location
Boston, MA
Type
conf
DOI
10.1109/CICC.1990.124837
Filename
124837
Link To Document