Title :
A compact DSP architecture for digital audio
Author :
Ryu, Changwon ; Park, Hyungbae ; Park, Jusung ; Kim, Kangjoo
Author_Institution :
Pusan Nat. Univ., Busan
fDate :
Nov. 30 2008-Dec. 3 2008
Abstract :
This paper describes the architecture and design procedure of a DSP (digital signal processor) for the digital audio applications. The suggested DSP has fixed 24 bit data structure, 6 stage pipeline, and 125 instructions. Some of the instructions are specially designed for the audio signal processing. The designed DSP has been verified by comparing the results from CBS (cycle based simulator) and those of HDL simulation through the single instruction set test, the instruction combination test, and real audio applications. Finally, we confirm by the HDL simulation that the DSP carried out successfully out ADPCM and MPEG-2 AAC decoding algorithm.
Keywords :
audio signal processing; digital signal processing chips; HDL simulation; audio signal processing; compact DSP architecture; digital audio application; digital signal processor; word length 24 bit; Data structures; Decoding; Digital signal processing; Digital signal processors; Hardware design languages; Pipelines; Process design; Signal design; Signal processing; Testing;
Conference_Titel :
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
Conference_Location :
Macao
Print_ISBN :
978-1-4244-2341-5
Electronic_ISBN :
978-1-4244-2342-2
DOI :
10.1109/APCCAS.2008.4746306
