Title :
Automatic verification of library-based IC designs
Author :
De Loore, B.S. ; Kostelijk, A.
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
Abstract :
A novel method for fully automatic verification of layout generated by means of a library is presented. It is based on the bottom-up reconstruction of the architecture level, starting from layout. The benefits have been confirmed during the verification of VLSI circuits generated with the PIRAMID silicon compiler. Previously unnoticed design and synthesis errors have been detected in a very efficient way
Keywords :
VLSI; circuit layout CAD; digital integrated circuits; fault location; PIRAMID silicon compiler; architecture level; automatic verification of layout; bottom-up reconstruction; design error detection; design verification automation; error identification; library-based IC designs; module verification; starting from layout; synthesis error detection; verification of VLSI circuits; Circuit simulation; Circuit synthesis; Design automation; Engines; Laboratories; Libraries; Pattern matching; Process design; Silicon compiler; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124838
