Title :
A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS
Author :
Nam, Jae-Won ; Jeon, Young-Deuk ; Cho, Young-Kyun ; Lee, Sang-Gug ; Kwon, Jong-Kee
Author_Institution :
Electron. & Telecommun. Res. Inst. (ETRI), Daejeon, South Korea
Abstract :
An 11-bit 20-MS/s algorithmic analog-to-digital converter (ADC) based on a dynamic biasing technique is proposed. A dynamic biasing technique is employed to an operational transconductance amplifier (OTA) for power reduction in sub-conversion stages. Besides, a distinct sampling clock scheme is taken to pre-amplifier for reducing aperture time errors. The prototype ADC is fabricated in a 65 nm 1P6M CMOS process and features a maximum signal-to-noise-ratio and a spurious-free-dynamic-range of 60.4 dB, and 69.2 dB at Nyquist input frequency with 20 MS/s from a 1.0 V supply, respectively. About 22% of OTA power dissipation is reduced without performance degradation and totally 2.85 mW is consumed.
Keywords :
CMOS integrated circuits; analogue-digital conversion; operational amplifiers; signal sampling; CMOS process; algorithmic ADC; analog-to-digital converter; aperture time error; dynamic biasing technique; operational transconductance amplifier; power 2.85 mW; sampling clock; size 65 nm; voltage 1 V; word length 11 bit; Analog-digital conversion; Apertures; CMOS process; Clocks; Operational amplifiers; Power amplifiers; Prototypes; Signal sampling; Signal to noise ratio; Transconductance;
Conference_Titel :
ESSCIRC, 2009. ESSCIRC '09. Proceedings of
Conference_Location :
Athens
Print_ISBN :
978-1-4244-4354-3
DOI :
10.1109/ESSCIRC.2009.5325946
