DocumentCode
2329232
Title
An Efficient Resource Planning For Semiconductor Manufacturing Lines Using Precise Simulation
Author
Nakamura, Shinji
Author_Institution
NTT LST Laboratories
fYear
1994
fDate
21-22 June 1994
Firstpage
68
Lastpage
71
Abstract
The large investment required for ASIC manufacturing lines makes it essential to minimize the turnaround time and work-in-process while improving machine utilization. For this purpose, we propose efficient planning method using lot capacity analysis models to estimate the rough numbers of each machine and discrete-event simulation that can reflect many details of actual lot processing and line operation. This paper describes how this can be used to optimize resources in the product mix with some special lot processing.
Keywords
Analytical models; Application specific integrated circuits; Capacity planning; Discrete event simulation; Fabrication; Investments; Manufacturing processes; Process planning; Semiconductor device manufacture; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing, 1994. Extended Abstracts of ISSM '94. 1994 International Symposium on
Conference_Location
Tokyo, Japan
Type
conf
DOI
10.1109/ISSM.1994.729426
Filename
729426
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