BSIM4-based lateral diode model for RF ESD applications

Poly gate defined lateral ESD diodes were fabricated, characterized and modeled using Foundry standard 65nm CMOS technology. Compare to conventional STI diode, the lateral diode demonstrated superior Q-factor and TLP IT2 due to the reduced transport distance and RC constant. Aided by BSIM4 MOS transistor model, a physically based scalable lateral diode model was developed and presented here for the first time. The accuracy of the diode model was validated with RF characterization data over a broad device geometrical range. The model was successfully used in LNA and ESD CDM protection co-design. A good match of LNA RF performance between Si-data and model prediction was achieved for N+/PW and P+/NW lateral diodes. Experimental results showed that LNA with lateral diode protection passed +/-500V ESD CDM zap voltage, while LNA with STI diode started to fail at only -250V.