A digitally calibrated 14-bit linear 100-MS/s pipelined ADC with wideband sampling frontend

A 14-bit 100-MS/s pipelined ADC in 0.18 mum 1P6M CMOS process is presented. A new sampling technique is introduced which achieves high linearity over wide bandwidth by eliminating the major sources of distortion at low and high input frequencies. The ADC uses digital background calibration, featuring a shuffled-dithering scheme, to obtain a DNL of +0.18/-0.18 LSB and an INL of +1.1/-0.6 LSB. It achieves over 85 dB SFDR and 65 dB SNDR within the first Nyquist zone, maintains over 74 dB SFDR and 63 dB SNDR for input signals up to 400 MHz and consumes 220 mW at 1.8 V supply.