DocumentCode :
2329439
Title :
A 19GHz, 250pJ/bit non-linear BPSK demodulator in 90nm CMOS
Author :
Macias-Montero, J.G. ; Yan, H. ; Akhnoukh, A. ; de Vreede, L.C.N. ; Long, J.R. ; Lopez-Villegas, J.M. ; Pekarik, J.J.
Author_Institution :
Electron. Res. Lab., Delft Univ. of Technol., Delft, Netherlands
fYear :
2009
fDate :
14-18 Sept. 2009
Firstpage :
304
Lastpage :
307
Abstract :
A low-complexity binary phase shift keying (BPSK) demodulator realizes ultra-low power operation without external components. Second harmonic injection-locking followed by analog multiplication is employed to recover data from a 19 GHz BPSK-modulated carrier. Measured bit error rate (BER) at 10 Mbps for the 0.35 mm2 testchip in 90 nm CMOS is comparable to classical DBPSK detection. The prototype demodulator consumes just 2.5 mW at 0.8 V, or 250 pJ/bit.
Keywords :
CMOS integrated circuits; demodulators; error statistics; phase shift keying; CMOS; analog multiplication; binary phase shift keying; bit error rate; frequency 19 GHz; nonlinear BPSK demodulator; power 2.5 mW; second harmonic injection-locking; size 90 nm; ultra low power operation; voltage 0.8 V; Binary phase shift keying; Bit error rate; Circuits; Demodulation; Frequency synchronization; Injection-locked oscillators; Power harmonic filters; Radio frequency; Robustness; Transceivers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ESSCIRC, 2009. ESSCIRC '09. Proceedings of
Conference_Location :
Athens
ISSN :
1930-8833
Print_ISBN :
978-1-4244-4354-3
Type :
conf
DOI :
10.1109/ESSCIRC.2009.5325959
Filename :
5325959
Link To Document :
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