Title :
A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving
Author :
Madoglio, P. ; Ravi, A. ; Cuellar, L. ; Pellerano, S. ; Seddighrad, P. ; Lomeli, I. ; Palaskas, Y.
Author_Institution :
Commun. Circuits Lab., Intel Corp., Hillsboro, OR, USA
Abstract :
A technique to implement time-interleaved digital DeltaSigma modulators using standard cells and digital synthesis tools is presented. Time interleaving allows clocking of the standard cell blocks at submultiples of the final sampling rate fs. Additional delay stages are used to segment the time-interleaved/pipelined MASH DeltaSigma topology into reduced complexity sub-blocks, each with independent critical paths. A prototype IC has been fabricated in digital CMOS 45 nm-LP: it has been validated at 2.5 GHz, while consuming 6.9 mW from a 1.1 V supply, and at 3.3 GHz increasing the nominal supply to 1.2 V.
Keywords :
CMOS digital integrated circuits; UHF integrated circuits; delta-sigma modulation; field effect MMIC; network topology; signal sampling; DeltaSigma modulator; IC fabrication; LP CMOS; digital CMOS; digital signal processing; digital synthesis tool; frequency 2.5 GHz; frequency 3.3 GHz; pipelined MASH DeltaSigma topology; power 6.9 mW; size 45 nm; time-interleaved digital modulator; voltage 1.1 V; voltage 1.2 V; Added delay; CMOS integrated circuits; Clocks; Delta modulation; Digital modulation; Interleaved codes; Multi-stage noise shaping; Prototypes; Sampling methods; Topology;
Conference_Titel :
ESSCIRC, 2009. ESSCIRC '09. Proceedings of
Conference_Location :
Athens
Print_ISBN :
978-1-4244-4354-3
DOI :
10.1109/ESSCIRC.2009.5325960
