An Integrated Failure Analysis Environment: An Experimental Model For Research And Development

The development of advanced integrated circuit processes requires a methodology for efficient reduction of defect density. Our methodology integrates standard electrical tests, novel test data analyses, and stripback to determine the physical causes for electrical faults. The process of observing defects with an optical microscope or SEM was made accurate and rapid by a computer controlled stage. This paper describes application of this environment using selected examples from the development of a 0.6 um CMOS process.