Title :
An 8th-order MASH delta-sigma with an OSR of 3
Author :
Caldwell, Trevor C. ; Johns, David A.
Author_Institution :
Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Abstract :
This paper demonstrates that a high-order MASH delta-sigma modulator with a very low oversampling ratio can attain performance similar to a pipelined converter. The delta-sigma architecture fabricated is an 8-stage cascade of 1st-order stages with an oversampling ratio of 3 and realized in a 0.18 mum CMOS process. The modulator attains an SNDR of 60 dB at a 50 MHz sampling frequency and an 8.33 MHz input bandwidth.
Keywords :
CMOS integrated circuits; delta-sigma modulation; 1st-order stages; 8-stage cascade; 8th-order MASH delta-sigma; CMOS; delta-sigma architecture; frequency 50 MHz; frequency 8.33 MHz; oversampling ratio; size 0.18 mum; Bandwidth; CMOS process; Circuits; Computer architecture; Delta modulation; Multi-stage noise shaping; Noise reduction; Noise shaping; Pipelines; Stability;
Conference_Titel :
ESSCIRC, 2009. ESSCIRC '09. Proceedings of
Conference_Location :
Athens
Print_ISBN :
978-1-4244-4354-3
DOI :
10.1109/ESSCIRC.2009.5325962
