Accurate Bit-Error-Rate estimation for efficient high speed I/O testing

We introduce a bit-error-rate (BER) estimation technique for high-speed serial links, which utilizes the jitter spectral information extracted from the transmitted data and some key characteristics of the clock and data recovery (CDR) circuit in the receiver. In addition to offering insight into both the behavior of the CDR loop and the contribution of the jitter to the BER, the estimation technique can be used to accelerate the jitter tolerance test by eliminating the conventional BER measurement process. We will discuss two different versions of the estimation technique: one for use with linear CDR circuits and the other for non-linear CDR circuits. Experimental results comparing the estimated BER and the measured BER demonstrate the high accuracy of the proposed technique.