Title :
A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead
Author :
Kao, Jerry C. ; Ma, Wei-Hsiang ; Sathe, Visvesh S. ; Papaefthymiou, Marios
Author_Institution :
Univ. of Michigan, Ann Arbor, MI, USA
Abstract :
We present a 14-tap 8-bit FIR chip designed using a novel charge-recovery logic family with only 1.5 cycles of additional latency over the best possible static CMOS design. Fabricated in a 0.13 mum CMOS process, the chip operates in the 365-600 MHz range with a 3 nH on-chip inductor. At its resonant frequency of 466 MHz, it dissipates 39.1 mW and recovers 45% of the energy supplied to it.
Keywords :
CMOS integrated circuits; FIR filters; inductors; integrated circuit manufacture; logic design; CMOS design; FIR filter; charge-recovery logic; frequency 365 MHz to 600 MHz; on-chip inductor; power 39.1 mW; size 0.13 mum; word length 8 bit; CMOS logic circuits; CMOS process; Clocks; Delay; Energy efficiency; Finite impulse response filter; Logic design; Logic devices; MOS devices; Resonant frequency; Charge-recovery logic; FIR filter;
Conference_Titel :
ESSCIRC, 2009. ESSCIRC '09. Proceedings of
Conference_Location :
Athens
Print_ISBN :
978-1-4244-4354-3
DOI :
10.1109/ESSCIRC.2009.5325975
