A Microprogrammable Memory Controller for high-performance dataflow applications

Author

Martin, Jérôme ; Bernard, Christian ; Clermidy, Fabien ; Durand, Yves

Author_Institution

CEA, MINATEC, Grenoble, France

fYear

2009

fDate

14-18 Sept. 2009

Firstpage

348

Lastpage

351

Abstract

High-performance embedded dataflow systems require intensive data manipulation involving synchronization, buffering, duplication and reordering. Our Microprogrammable Memory Controller (MMC) is designed to handle these tasks more efficiently than the data processing cores. Dataflow management for several computing cores is combined in a single MMC. This reduces the global complexity and memory of the system. The MMC has been implemented in a 65nm low-power CMOS integrated circuit for baseband processing of OFDMA communications. It achieves a bandwidth of 24.6 Gbps @385 MHz, with an average 38 mW power consumption.

Keywords

buffer storage; data flow computing; embedded systems; integrated circuit design; microcontrollers; microprogramming; programmable circuits; synchronisation; system-on-chip; MMC design; OFDMA communication; bandwidth 385 MHz; baseband processing; bit rate 24.6 Gbit/s; data buffering; data duplication; data processing core; data reordering; data synchronization; global complexity reduction; high-performance embedded dataflow management system; intensive data manipulation; logical buffer; low-power CMOS integrated circuit; memory reduction; microprogrammable memory controller; power 38 mW; power consumption; size 65 nm; system-on-chip; Bandwidth; Baseband; Buffer storage; CMOS integrated circuits; Communication system control; Control systems; Data processing; Power system management; Random access memory; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC, 2009. ESSCIRC '09. Proceedings of

Conference_Location

Athens

ISSN

1930-8833

Print_ISBN

978-1-4244-4354-3

Type

conf

DOI

10.1109/ESSCIRC.2009.5325981

Filename

5325981