Title :
An efficient logic block interconnect architecture for user-reprogrammable gate array
Author :
Kawana, Keiichi ; Keida, Hisaya ; Sakamoto, Makoto ; Shibata, Keiji ; Moriyama, Ichiro
Author_Institution :
Kawasaki Steel Corp., Chiba, Japan
Abstract :
A novel architecture for an SRAM-based user-reprogrammable gate array which consists of programmable logic elements (PLEs), switching stations (SSs), wirings, and input/output blocks (IOBs) is discussed. The SS is designed to connect its neighboring PLEs and/or IOBs through only one NMOS pass transistor to maintain a sufficient signal level and reduce the delay in signal propagation. Hidden interconnection networks which directly merge neighboring PLEs were adopted to expand the number of inputs and product terms of combinational logic, and allow the construction of a parallel-to-serial/serial-to-parallel converter without using SSs. A fabricated CMOS prototype chip includes an 8 Kbit 50 ns temporary storage memory which is programmable to the random access mode or the FIFO mode with a word length of 4 bit or 8 bit
Keywords :
CMOS integrated circuits; logic arrays; 4 bit; 50 ns; 8 bit; 8 kbit; FIFO mode; NMOS pass transistor; PLD; SRAM-based gate array; combinational logic; hidden interconnection network; input/output blocks; logic block interconnect architecture; parallel-to-serial/serial-to-parallel converter; programmable logic devices; programmable logic elements; prototype chip; random access mode; switching stations; temporary storage memory; user-reprogrammable gate array; wirings; word length; Circuits; Flip-flops; Logic arrays; Logic devices; Programmable logic arrays; Programmable logic devices; Random access memory; Switches; Testing; Wiring;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124842
