DocumentCode :
2329929
Title :
Trends in design of massively parallel coprocessors implemented in digital ASICs
Author :
Földesy, Péter
Author_Institution :
Lab. of Analogic & Neural Comput., Hungarian Acad. of Sci., Budapest, Hungary
Volume :
4
fYear :
2004
fDate :
25-29 July 2004
Firstpage :
3131
Abstract :
This paper collects the most recent parallel coprocessors and highlights the recent trends. It is shown that the single chip massively parallel processor implementations seem to disappear from the scientific investigations (with the exception of low-level near-sensor image processing). Meanwhile, the formerly developed architectures have moved inside complex system-on-chips/microprocessors. The common aspect of the recent architectures is the advanced processing element and internal interconnection solutions, and the dominant mid-grain parallelism (i.e. up to a hundred processing element per chip).
Keywords :
digital signal processing chips; parallel processing; system-on-chip; application specific integrated circuits; complex system-on-chips; digital ASICs; dominant midgrain parallelism; massively parallel coprocessors; Application specific integrated circuits; Automation; Concurrent computing; Coprocessors; Image processing; Laboratories; Parallel processing; Radar signal processing; Signal processing algorithms; Systolic arrays;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on
Conference_Location :
Budapest
ISSN :
1098-7576
Print_ISBN :
0-7803-8359-1
Type :
conf
DOI :
10.1109/IJCNN.2004.1381174
Filename :
1381174
Link To Document :
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