DocumentCode :
2329934
Title :
Low-complexity shift-LDPC decoder for high-speed communication systems
Author :
Zhang, Chuan ; Li, Li ; Lin, Jun ; Wang, Zhongfeng
Author_Institution :
Inst. of VLSI Design, Nanjing Univ., Nanjing
fYear :
2008
fDate :
Nov. 30 2008-Dec. 3 2008
Firstpage :
1636
Lastpage :
1639
Abstract :
In this paper, an efficient high-speed low-density parity-check (LDPC) decoder is presented. Single minimum decoding and non-uniform quantization schemes are explored to reduce the complexity of computation core and the memory requirement. Shifting structure is incorporated to significantly reduce the routing complexity of the LDPC decoder. The implementation of an 8192-bit LDPC decoder demonstrates that about 63.3% hardware reduction can be achieved compared with the state-of-the-art design for high speed LDPC decoding. It is also shown that, using SMIC 0.18 mum CMOS technology, 5.4 Gb/s decoding throughput can be obtained at 15 decoding iterations.
Keywords :
CMOS integrated circuits; computational complexity; decoding; integrated circuit design; parity check codes; 8192-bit LDPC decoder; SMIC CMOS technology; computation complexity; hardware reduction; high-speed communication systems; high-speed low-density parity-check decoding; low-complexity shift-LDPC decoder; nonuniform quantization schemes; state-of-the-art design; Bit error rate; CMOS technology; Hardware; Iterative decoding; Parity check codes; Quantization; Routing; Silicon; Throughput; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
Conference_Location :
Macao
Print_ISBN :
978-1-4244-2341-5
Electronic_ISBN :
978-1-4244-2342-2
Type :
conf
DOI :
10.1109/APCCAS.2008.4746350
Filename :
4746350
Link To Document :
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