Title :
Application Of A Graph Description Method For Structural And Electrical Analysis Of VLSIs
Author :
Ochiai, Katsuyuki ; Tazawa, Satoshi ; Nakajima, Shigeru
Author_Institution :
NTT LSI Laboratories
Abstract :
A graph description method is proposed to describe layout pattern data. The Graph can express not only pattern positions but also physical attributes of the patterns. Therefore, the data processing time for structural recognition of LSI is less than a method dealing with pattern data of vertex coordinates directly.
Keywords :
Capacitance; Data processing; Failure analysis; Information analysis; Laboratories; Large scale integration; Pattern analysis; Pattern recognition; Scanning electron microscopy; Very large scale integration;
Conference_Titel :
Semiconductor Manufacturing, 1994. Extended Abstracts of ISSM '94. 1994 International Symposium on
Conference_Location :
Tokyo, Japan
DOI :
10.1109/ISSM.1994.729463
