FPGA implementation of the kernel CMAC

Cerebellar model articulation controller (CMAC) neural network is a real alternative to MLP and RBF and has some advantageous features: its training is fast and its architecture is especially suitable for digital hardware implementation. The price of these attractive features is its rather poor capability. The poor capability can be improved if a recently proposed regularization and/or a kernel version of the CMAC is used. The paper presents the first results of a study about the efficient hardware realization of various versions of CMAC. Three versions have been developed: the classical Albus CMAC, its regularized version, which has better generalization capability and a kernel CMAC. The solutions, that were developed using high-level synthesis (Handel C), are based on Virtex FPGA.