Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?

Author

Chiarella, T. ; Witters, L. ; Mercha, A. ; Kerner, C. ; Dittrich, R. ; Rakowski, M. ; Ortolland, C. ; Ragnarsson, L. Å ; Parvais, B. ; De Keersgieter, A. ; Kubicek, S. ; Redolfi, A. ; Rooyackers, R. ; Vrancken, C. ; Brus, S. ; Lauwers, A. ; Absil, P. ; Bi

Author_Institution

IMEC, Leuven, Belgium

fYear

2009

fDate

14-18 Sept. 2009

Firstpage

84

Lastpage

87

Abstract

The multi-gate architecture is considered as a key enabler for further CMOS scaling. FinFETs can readily be manufactured on SOI or bulk substrates. We report for the first time an extensive benchmark of their critical electrical figures of merit. Both alternatives show better scalability than PLANAR CMOS and exhibit similar intrinsic device performance. Introducing SOI substrates and low doped fins results in lower junction capacitance, higher mobility and voltage gain with reduced mismatch. Using an optimized integration to minimize parasitics we demonstrate high-performing FinFET ring-oscillators with delays down to 10 ps/stage for both SOI and bulk FinFETs and working SRAM cells at VDD = 1.0 V.

Keywords

CMOS integrated circuits; MOSFET; SRAM chips; benchmark testing; oscillators; semiconductor doping; silicon-on-insulator; CMOS scaling; FinFET; SOI substrate; benchmark; bulk substrate; critical electrical figures-of-merit; device mismatch; device mobility; doped fins; intrinsic device performance; junction capacitance; multigate architecture; optimized integration; parasitic minimization; ring-oscillators; voltage gain; working SRAM cells; Delay; Doping; Electrodes; FinFETs; Geometry; High K dielectric materials; High-K gate dielectrics; Implants; Parasitic capacitance; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC, 2009. ESSCIRC '09. Proceedings of

Conference_Location

Athens

ISSN

1930-8833

Print_ISBN

978-1-4244-4354-3

Type

conf

DOI

10.1109/ESSCIRC.2009.5325993

Filename

5325993