Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below

Author

Fenouillet-Beranger, C. ; Perreau, P. ; Denorme, S. ; Tosti, L. ; Andrieu, F. ; Weber, O. ; Barnola, S. ; Arvet, C. ; Campidelli, Y. ; Haendler, S. ; Beneyton, R. ; Perrot, C. ; de Buttet, C. ; Gros, P. ; Pham-Nguyen, L. ; Leverd, F. ; Gouraud, P. ; Abbat

Author_Institution

CEA-LETI Minatec, Grenoble, France

fYear

2009

fDate

14-18 Sept. 2009

Firstpage

88

Lastpage

91

Abstract

In this paper we explore for the first time the impact of an Ultra-Thin BOX (UTBOX) with and without Ground Plane (GP) on a 32 nm Fully-Depleted SOI (FDSOI) high-k/metal gate technology. The performance comparison versus thick BOX architecture exhibits a 50 mV DIBL reduction by using 10 nm BOX thickness for NMOS and PMOS devices at 33 nm gate length. Moreover, the combination of DIBL reduction and threshold voltage modulation by adding GP enables to reduce the Isb current by a factor 2.8 on a 0.299 mum² SRAM cell while maintaining an SNM of 296 mV @ Vdd 1.1 V.

Keywords

MOS integrated circuits; SRAM chips; silicon-on-insulator; DIBL reduction; FDSOI devices; NMOS devices; PMOS devices; SRAM cell; fully-depleted SOI; ground plane; high-k/metal gate technology; size 10 nm; size 32 nm; size 33 nm; ultra-thin BOX; voltage 1.1 V; voltage 296 mV; voltage 50 mV; Epitaxial growth; Fabrication; High K dielectric materials; High-K gate dielectrics; MOS devices; Oxidation; Random access memory; Silicon on insulator technology; Threshold voltage; Wet etching;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC, 2009. ESSCIRC '09. Proceedings of

Conference_Location

Athens

ISSN

1930-8833

Print_ISBN

978-1-4244-4354-3

Type

conf

DOI

10.1109/ESSCIRC.2009.5325994

Filename

5325994