DocumentCode :
2330061
Title :
Design of simple and high speed VLSI core for the protection of mass storages
Author :
Jing, Ming-Haw ; Chen, Zih-Heng ; Chen, Jian-Hong ; Cheng-Yi Wu
Author_Institution :
Dept. of Inf. Eng., I-Shou Univ., Kaohsiung
fYear :
2008
fDate :
Nov. 30 2008-Dec. 3 2008
Firstpage :
1660
Lastpage :
1663
Abstract :
This paper presents a research to strengthen the using of embedded system memory, including: Flash memory, SRAM, DRAM etc. For increasing the reliability on data storage, we use the conventional fault-tolerant mechanisms-Mirror and CRC techniques to carry out the forward protection at first. Furthermore we use the encryption and Reed-Solomon code to improve the function at back end. This article designs a simple and high speed solution based on the finite field arithmetic, let the fault-tolerant facility can tolerate one-bit error from multiple bit error or multiple column error on common memories. Then we advanced improve the speed problem of Reed-Solomon code in coding, and develop an efficient way in the VLSI architecture. Finally we adopt the embedded system of DE2 to develop the co-design coding environment to provide a complete and high reliability scheme.
Keywords :
DRAM chips; Reed-Solomon codes; SRAM chips; VLSI; cyclic redundancy check codes; fault tolerant computing; flash memories; DRAM; Reed-Solomon code; SRAM; VLSI core; cyclic redundancy check codes; data storage protection; encryption; fault-tolerant facility; finite field arithmetic; flash memory; forward protection; Cryptography; Cyclic redundancy check; Embedded system; Fault tolerance; Flash memory; Galois fields; Protection; Random access memory; Reed-Solomon codes; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
Conference_Location :
Macao
Print_ISBN :
978-1-4244-2341-5
Electronic_ISBN :
978-1-4244-2342-2
Type :
conf
DOI :
10.1109/APCCAS.2008.4746356
Filename :
4746356
Link To Document :
بازگشت