A low power, area efficient limiting amplifier in 90nm CMOS

Author

Tavernier, Filip ; Steyaert, Michiel

Author_Institution

ESAT-MICAS, K.U. Leuven, Heverlee, Belgium

fYear

2009

fDate

14-18 Sept. 2009

Firstpage

128

Lastpage

131

Abstract

A low power limiting amplifier with area efficient offset compensation in 90 nm CMOS is presented. The large time constant needed in the offset compensation feedback loop is boosted by an inverting amplifier to reduce the chip area. On top of this, to reduce the chip area even more, negative capacitors are applied to increase the bandwidth instead of making use of the inductive peaking technique. The proposed circuit has a small-signal gain of 35 dB and a bandwidth of 4.15 GHz. The input sensitivity for a BER of 10^-12 is 2.75 mV, 2.9 mV and 3.75 mV for a bitrate of 3, 4 and 5 Gbit/s respectively. The power consumption is only 14.7 mW and the area of the circuit is 0.12 mm².

Keywords

CMOS integrated circuits; compensation; error statistics; feedback amplifiers; low-power electronics; microwave amplifiers; BER; CMOS; bandwidth 4.15 GHz; bit rate 3 Gbit/s; bit rate 4 Gbit/s; bit rate 5 Gbit/s; gain 35 dB; inductive peaking technique; inverting amplifier; low-power limiting amplifier; offset compensation feedback loop; power 14.7 mW; power consumption; size 90 nm; voltage 2.75 mV; voltage 2.9 mV; voltage 3.75 mV; Bandwidth; Capacitors; Circuit topology; Clocks; Energy consumption; Limiting; Optical amplifiers; Optical receivers; Power amplifiers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC, 2009. ESSCIRC '09. Proceedings of

Conference_Location

Athens

ISSN

1930-8833

Print_ISBN

978-1-4244-4354-3

Type

conf

DOI

10.1109/ESSCIRC.2009.5325997

Filename

5325997