A low power, area efficient limiting amplifier in 90nm CMOS

A low power limiting amplifier with area efficient offset compensation in 90 nm CMOS is presented. The large time constant needed in the offset compensation feedback loop is boosted by an inverting amplifier to reduce the chip area. On top of this, to reduce the chip area even more, negative capacitors are applied to increase the bandwidth instead of making use of the inductive peaking technique. The proposed circuit has a small-signal gain of 35 dB and a bandwidth of 4.15 GHz. The input sensitivity for a BER of 10^-12 is 2.75 mV, 2.9 mV and 3.75 mV for a bitrate of 3, 4 and 5 Gbit/s respectively. The power consumption is only 14.7 mW and the area of the circuit is 0.12 mm².