Static leakage current estimation of on-the-fly generated IP logic blocks

This paper introduces a new approach to pattern dependent static current estimation in logic blocks. A static current model is first developed at the transistor level and then extended to the logic gate level and logic block level. Using these static current models, a methodology has been introduced to estimate static power dissipation of logic blocks in a library-free design environment, in which the cells are generated and sized dasiaon the flypsila, driven by specification and targeted technology. Across several MCNC benchmarks, the worst case mean accuracy of the estimation methodology compared to SPICE is 2.4%. The runtime of the proposed methodology was also on average 43 times faster than SPICE.