An FPGA family optimized for high densities and reduced routing delay

Author

Ahrens, Mike ; Gamal, Abbas ; Galbraith, Doug ; Greene, Jonathan ; Kaptanoglu, Sinan ; Dharmarajan, K. ; Hutchings, Lynn ; Ku, Sifuei ; McGibney, Phil ; McGowan, John ; Sanie, A. ; Shaw, Kitty ; Stiawalt, Norma ; Whitney, Telle ; Wong, Tom ; Wong, Wayne ;

Author_Institution

Actel Corp., Sunnyvale, CA, USA

fYear

1990

fDate

13-16 May 1990

Abstract

The Act-2 family of CMOS field-programmable gate arrays (FPGAs) uses an electrically programmable antifuse and novel architectural and circuit features to obtain higher logic densities while increasing speed and routability. Improvements include: two new logic modules, novel I/O and clock driver circuitry, and more flexible and faster routing paths. New addressing circuitry shortens programming time and speeds complete testing for shorts, opens, and stuck-at faults. Fully automatic placement and complete routing are retrained. Special software tools used for architectural exploration and layout generation are discussed

Keywords

CMOS integrated circuits; VLSI; logic arrays; Act-2 family; CMOS; FPGA family; I/O circuitry; PLD; addressing circuitry; architectural exploration; circuit features; clock driver circuitry; densities; electrically programmable antifuse; field-programmable gate arrays; layout generation; logic modules; programmable logic devices; reduced routing delay; routability; CMOS logic circuits; Circuit testing; Clocks; Driver circuits; Field programmable gate arrays; Flexible printed circuits; Logic circuits; Logic programming; Programmable logic arrays; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Conference_Location

Boston, MA

Type

conf

DOI

10.1109/CICC.1990.124844

Filename

124844