Asymmetric dual-gate multi-fin keeper bias options and optimization for low power and robust FinFET domino logic

A variable threshold voltage keeper circuit technique using independent-gate FinFET technology is proposed in this paper for simultaneous power reduction and speed enhancement in domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The optimum independent-gate keeper gate bias conditions are identified for achieving maximum savings in delay and power consumption while maintaining identical noise immunity as compared to the standard tied-gate FinFET domino circuits. With the variable threshold voltage asymmetric double-gate keeper circuit technique the evaluation speed is enhanced by up to 49% while reducing the power consumption by up to 46% as compared to a standard domino logic circuit designed for similar noise margin in a 32 nm FinFET technology.