A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit

The AES algorithm published in 2001 is now the most popular symmetric encryption algorithm. Several implementations have beed proposed but few of them considered the hardware cost and the throughput as a whole. This paper presents an AES core to be capable of both encryption and decryption with three different key lengths: 128-, 192-, and 256-bit. The overall hardware cost was optimized by a very compact on-the-fly key expansion unit and a highly integrated encryption/decryption datapath. The compact on-the-fly key expansion unit is achieved by sharing expansion processes of different key lengths. The integrated data datapath shares hardware resources between encryption and decryption. After manufactured in 90 nm CMOS technology, the area of the chip is 15,577 equivalent gates with throughput up to 1.69 Gb/s operating at 131.8 MHz.