BIST approach for testing configurable logic and memory resources in FPGAs

This paper presents a built-in self-test (BIST) approach for testing configurable logic and memory resources in Xilinx Virtex FPGAs using hard-macro. The resources under test include the configurable logic blocks (CLBs) and block random access memories (BRAMs) in all of their modes of operation. The proposed approach completely detects and diagnoses single and multiple stuck-at gate-level faults of the logic resources, and completely tests any address and data bus widths of configurable memory resources. Only 37 total test configurations (24 for logic BIST, 13 for RAMs BIST) are required while retrieving the BIST results using scan chain method.