A technique of automatic monitor generation based on FSM

Aiming at the requirements of real-time ability and good observability of result-checking in IC functional verification, a method was proposed to generate monitors automatically. Based on the requirements of the design property to be monitored, a sub-set was defined from the Property Specification Language (PSL), so that the objects to be monitored can be formally described. Based on the formal descriptions, monitors can be generated automatically through a two-step method. The formal descriptions are transferred into event sequences first. Then monitors are generated based on the event sequences through the method of FSM automatic construction. Mathematical model of the relationship between event sequence and FSM state evolving was put forward. Directed random analysis was applied in several serial interfaces to prove the effectiveness of our method. The results of analysis and the application based testing shows that the method proposed in this paper achieves better tradeoff between complex design property monitoring and the easiness to be mastered by verification engineers.