DocumentCode :
2330647
Title :
Power reduction techniques for an 8-core xeon® processor
Author :
Rusu, Stefan ; Tam, Simon ; Muljono, Harry ; Stinson, Jason ; Ayers, David ; Chang, Jonathan ; Varada, Raj ; Ratta, Matt ; Kottapalli, Sailesh ; Vora, Sujal
Author_Institution :
Intel Corp., Santa Clara, CA, USA
fYear :
2009
fDate :
14-18 Sept. 2009
Firstpage :
340
Lastpage :
343
Abstract :
This paper presents the power reduction and management techniques for the 45 nm, 8-core Nehalem-EX processor. Multiple clock and voltage domains are used to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors from the same silicon die. Clock and power gating minimize power consumed by disabled blocks. An on-die microcontroller manages voltage and frequency operating points, as well as power and thermal events. Idle power is reduced by shutting off the un-terminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency.
Keywords :
microcontrollers; parallel architectures; power aware computing; system recovery; 8-core Nehalem-EX processor; 8-core Xeonreg processor; cache recovery; cache sleep mode; core recovery; long channel devices; on-die microcontroller; power conversion efficiency; power gating; power reduction techniques; size 45 nm; voltage regulator; Clocks; Energy consumption; Energy management; Frequency; Manufacturing; Microcontrollers; Regulators; Silicon; Thermal management; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ESSCIRC, 2009. ESSCIRC '09. Proceedings of
Conference_Location :
Athens
ISSN :
1930-8833
Print_ISBN :
978-1-4244-4354-3
Type :
conf
DOI :
10.1109/ESSCIRC.2009.5326028
Filename :
5326028
Link To Document :
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