Compressor tree based processing element optimization in propagate partial SAD architecture

In H.264/AVC standard, the improvement of motion estimation (ME) part helps to enhance the performance greatly. However, the ME part, especially the integer motion estimation (IME) occupies computation complexity dramatically, which leads to complexity in hardware implementation. Many works have been done to achieve efficient IME engine and propagate partial SAD (PPSAD) architecture is the most efficient one in data path and hardware cost. Based on PPSAD structure, this paper proposes a compressor tree based compact PE array architecture. The 4-2 and 3-2 compressor trees are used to build up this compact structure. The proposed structure is embedded into PPSAD architecture and synthesized under different frequency points. With TSMC 0.18 mum 1P8M technology, the proposed architecture can achieve 10%-13% hardware cost reduction for a single 4times4 PE array compared with most recent work. About 10.7 k, 13.2 k and 6.5 k gates hardware cost can be saved compared with previous PPSAD structures.