A single bit 6.8mW 10MHz power-optimized continuous-time ΔΣ with 67dB DR in 90nm CMOS

Author

Crombez, Pieter ; Van der Plas, Geert ; Steyaert, Michiel ; Craninckx, Jan

Author_Institution

IMEC-SSET-Wireless, Leuven, Belgium

fYear

2009

fDate

14-18 Sept. 2009

Firstpage

336

Lastpage

339

Abstract

High data rates and increased digitization require A/D converters with high dynamic range and bandwidth. In combination with low power consumption they are key for broadband wireless systems. A single bit continuous-time DeltaSigma modulator with 10 MHz signal bandwidth avoiding high speed DEM circuits in 1.2V 90 nm digital CMOS is presented. It achieves an SNDR of 65 dB while consuming only 6.8 mW of power thanks to a global optimization at both architectural and circuit level. An overall energy efficiency of 0.24 pJ/conv is obtained by employing linearity enhanced integrators, a threshold configurable comparator enabling perfect loop delay compensation and low sensitive DAC integration.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); continuous time systems; delta-sigma modulation; low-power electronics; A/D converters; CMOS technology; bandwidth 10 MHz; continuous-time delta-sigma modulators; delay compensation; dynamic range; power 6.8 mW; size 90 nm; threshold configurable comparator; voltage 1.2 V; Bandwidth; CMOS technology; Circuits; Delay; Digital modulation; Dynamic range; Energy consumption; Filters; Linearity; Programmable logic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC, 2009. ESSCIRC '09. Proceedings of

Conference_Location

Athens

ISSN

1930-8833

Print_ISBN

978-1-4244-4354-3

Type

conf

DOI

10.1109/ESSCIRC.2009.5326032

Filename

5326032