A new modulo-N based digital clock synthesizer with an adjustable duty-cycle

A new architecture of digital clock synthesizer with an adjustable duty-cycle is designed. In the new architecture, a set of reference clocks with the same frequency but different phases is passed through a multiplexer (Mux) that is combined with an incrementer to output the maximal frequency to a modulo-N counter, where two frequency control words (FCWs) are used for the duty-cycle setting. A Gray encoder is designed to eliminate the glitch problem of the multiplexer. The function and performance of the synthesizer are validated via implementation and timing simulations with the TSMC 0.18 mum cell-based library.