Title :
Implementation of reconfigurable SHA-2 hardware core
Author :
Mladenov, Todor ; Nooshabadi, Saeid
Author_Institution :
Dept. of Inf. & Telecommun., Gwangju Inst. of Sci. & Technol., Gwangju
fDate :
Nov. 30 2008-Dec. 3 2008
Abstract :
Secure Hashing Algorithm (SHA) is increasingly becoming popular for the online security applications, specifically, for mobile and embedded system platforms. This necessitates a high performance hardware implementation of the four most utilized SHA algorithms (SHA-224, SHA-256, SHA-384, SHA-512). This paper presents a reconfigurable SHA-2 IP core utilizing the available hardware for computing SHA-384/ SHA-512 and SHA-224/ SHA-256 with double the throughput.
Keywords :
cryptography; file organisation; mobile-embedded system platforms; online security applications; reconfigurable SHA-2 IP core; reconfigurable SHA-2 hardware core; secure hashing algorithm; Digital signatures; Embedded system; Field programmable gate arrays; Hardware; Information security; Message authentication; NIST; Random number generation; Testing; Throughput;
Conference_Titel :
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
Conference_Location :
Macao
Print_ISBN :
978-1-4244-2341-5
Electronic_ISBN :
978-1-4244-2342-2
DOI :
10.1109/APCCAS.2008.4746392
