DocumentCode
2330798
Title
High throughput 32-bit AES implementation in FPGA
Author
Chang, Chi-Jeng ; Huang, Chi-Wu ; Chang, Kuo-Huang ; Chen, Yi-Cheng ; Hsieh, Chung-Cheng
Author_Institution
Inst. of Appl. Electron. Technol., Nat. Taiwan Normal Univ., Taipei
fYear
2008
fDate
Nov. 30 2008-Dec. 3 2008
Firstpage
1806
Lastpage
1809
Abstract
Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput (over several tens Gbps). However, low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 156 slices and a throughput of 876 Mbps, which outperformed the best reported result of 648 Mbps throughput found in literature.
Keywords
application specific integrated circuits; cryptography; field programmable gate arrays; advance encryption standard; application specific integrated circuits; bit rate 648 Mbit/s; bit rate 876 Mbit/s; field programmable gate arrays; word length 32 bit; Circuits; Clocks; Educational technology; Electronics industry; Field programmable gate arrays; Hardware; Industrial electronics; Shift registers; Table lookup; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
Conference_Location
Macao
Print_ISBN
978-1-4244-2341-5
Electronic_ISBN
978-1-4244-2342-2
Type
conf
DOI
10.1109/APCCAS.2008.4746393
Filename
4746393
Link To Document